A flash memory device typically includes a core area and a periphery area. The core area includes memory transistors, while the periphery area contains both low-voltage transistors for handling logic and switching circuitry, and high-voltage transistors for handling high-voltages encountered during flash memory programming and erase operations.
FIG. 1 is a top view of a portion of a conventional NAND flash memory device 10 The flash memory device 10 includes a core area 12 and a periphery area 14. The core area 12 includes an array of memory transistors 16 and two select gate regions that include a row of select transistors connected by a select word-line 28. One select gate region is referred to as a select drain gate region 18 and the other select gate region is referred to as a select source gate region 20. Although not shown, the periphery area 14 contains low-voltage transistors for handling logic and switching circuitry, and high-voltage transistors for handling high-voltages encountered during flash memory programming and erase operations.
The memory transistors 16 are stacked gate structures that include a layer of type-1 polysilicon (polyl) 22 that form floating gates, and a layer of type-2 polysilicon (poly2) that forms word-lines 26 interconnecting a row of memory transistors 16. The select transistors in the select gate regions 18 and 20 are single gate structures comprising a layer of polyl 22, which also forms the select word-line 28 connecting the select gate transistors. Fabricating such an device is a multi-step process.
FIG. 2 is a flow chart illustrating conventional process steps required to fabricate a flash memory device 10. Also shown is a series of cross sectional views (FIGS. 2(a–g)) of a substrate showing the resulting structure.
First a dual core gate oxide is performed, via step 40. Typically a dual core gate oxide is implemented to fabricate oxide layers of different thickness in the core area. Next, a nitridation process is performed, via step 42. This is done to improve the reliability of the core gate oxide. Typically, the nitridation process involves the introduction of nitrogen to the Si-SiO2 interface in the core and periphery areas. Next, a layer of type-1 polysilicon (poly1) is deposited in both the core area and periphery area, via step 44. After the poly1 is patterned, a layer of oxide nitride oxide (ONO) is deposited over the poly1 layer, via step 46.
After the layer of ONO is deposited, the core area is covered by photo resist and the ONO and poly1 layer is removed in the periphery area, via step 48. Then, a dual periphery gate oxide is performed, via step 50. Finally, a type-2 layer of polysilicon (poly2) is deposited in all areas and the gate stacks are formed, via step 52.
As previously mentioned, a nitridation process is performed after the dual core gate oxide in order to improve the reliability of the core gate oxide. However, when the nitridation process is performed, nitrogen is also introduced in the periphery area. Because the presence of nitrogen residue in the periphery area inhibits the subsequent growth of oxide in the periphery area, the quality of the dual periphery gate oxide is problematic based on the existence of defects related to the nitrogen residue.
Consequently, the nitrogen contamination problem is a technically difficult issue that hinders the implementation of nitridation in the flash memory fabrication process. Therefore, the reliability of the core gate oxide and thus the reliability of the flash memory device, becomes more of a concern. Several techniques, such as reoxidation treatment after nitridation or using a hard mask to cover the periphery area during nitridation have been used. However, these methods complicate the process and introduce some side effects as well.
Accordingly, an improved method of fabricating a flash memory device is needed. The method should be cost effective, easy to implement and shouldn't add undue complexity to existing fabrication methods. The present invention addresses such a need.